DMX Receiver

The typical method of generating a DMX512 signal is setting a UART to 250Kbps. Drive the UART line low for a break, then start sending 513 bytes. Since the rate is fixed you can use a timer to determine when you can start another break and data frame. Alternately, loop the output into the UART input and wait until you've received all the data you just sent.

An example receiver algorithm is described below.

Most (all?) DMX controllers are based on microcontrollers. Various devices can be used, one common controller is the AT-Mega AVR. This device provides many I/O pins that can directly drive equipment, minimising the need for external logic. A typical software design comprises 4 basic modules:

The algorithm provides the input processing for reception of a DMX frame to create a set of DMX values, stored in the array DMXField[]. The algorithm is triggered as an Interrupt Service Routine (ISR), for each byte received. from a Universal Asynchronous Serial Receiver/Transmitter (USART).

A global variable, gDMXState, is used to record progress through the received frame.

Most devices use a combination of adjacent slot values to signal to a receiver. The algorithm collects the value of the slots in the array DMXRXField[]. The contents of this array may be used by a parallel thread to generate the ouput levels.

More generally, the control values accumulated may be used in many different ways:

The algorithm above cycles through 6 internal states to process frames with a start code of zero:

Each receiver device is supposed to hold their last setting for up to 1 second if the signal stop being received. There is no checksum or error correction of any kind. You may note that for lighting this is ok, if a light has been getting 0 for the last few seconds, and suddenly gets a 128 due to noise, it doesn't have time to change brightness noticeably before the next value comes. Therefore it is to be used only for non-critical systems (i.e., no dangerous equipment).

Prof. Gorry Fairhurst, School of Engineering, University of Aberdeen, Scotland.